1. Field of the Invention
The present invention relates in general to a precharge approach for semiconductor memories, such as Synchronous Dynamic Random Access Memories (SDRAMs), and more specifically, to a SDRAM that can segmentally precharge each bank in the SDRAM and then shorten memory access latency.
2. Description of the Prior Art
Semiconductor memory devices are widely used as a main storage media in many electronic systems, especially in computer systems. Static Random Access Memories (SRAMs) and Dynamic Random Access Memories (DRAMs) are two examples of these semiconductor memory devices, in which the DRAMs have a lower price and primarily serve as the main memory devices in computer systems, while SRAMs have a faster access speed than the DRAMs and usually serve as cache memory for bridging the operation speed between a microprocessor and the DRAM main memory.
With the increasing operation speed of microprocessors, the speed mismatch between the processors and the DRAMs is significant and has a severe impact on the system performance. Conventional DRAMs employ an operation mode called Fast Page Mode (FPM), in which memory in a page given by a specific row address can be randomly accessed. For increasing the operation speed, a new operation mode called Extended Data Output (EDO) has been applied in DRAM products. In EDO DRAMs, performance improvement is achieved by extending the data valid time until the next data drives the memory bus. EDO DRAMs have a 30.about.40% speed improvement. However, this still can not keep up with the requirement of the increasing processor speed.
Synchronous DRAMs employ a bursting technique to overcome such a speed limitation. When a first page address has been accessed, the SDRAM can predict the address of the memory location to be accessed. Such an address prediction scheme eliminates the delay associated with detecting and latching an externally provided address into the SDRAM. Using SDRAMs, users must previously set several parameters of SDRAMs before any read and write commands. First, parameters of burst length (sometimes abbreviated as BL) and burst type must be defined to the SDRAM. The burst length is used to define the number of bits associated with this access operation. Thus, an internal address counter can properly and timely generate the next memory location to be accessed according to the starting access address and the burst length during the following access operations. The burst type is used to decide whether the address counter is to provide sequential ascending page addresses or interleaved page addresses within the defined burst length. In addition, a parameter of CAS latency is also previously set before read commands, to decide the delay from when a read command is registered on a rising clock edge to when the data from that read command becomes available at the outputs.
FIG. 1 (PRIOR ART) schematically illustrates a blocking diagram of a common SDRAM architecture. Usually, SDRAMs employ a two-bank architecture, as shown in FIG. 1, for hiding row precharge and first access delays by alternately opening (interleaving) the two memory banks. CLK represents the system clock input and all SDRAM inputs are sampled at the rising edges of this clock. The CKE signal is used to activate or deactivate the CLK signal when high or low, respectively. A0.about.A9, A10 and A11 (or called BANK SELECT, BS) represent the address signals, in which the BS signal is used to select the accessed memory bank. In addition, CS# represents the chip select signal (active low), RAS# represents the row address strobe signal (active low), CAS# represents the column address strobe signal (active low) and WE# represents the write enable signal (active low). These four signals are used to set the operation mode of SDRAM 10.
The CLK signal is fed to all components in DRAM 10 for synchronizing the operation. The combination of these control signals fed to command decoder 20 is used as the operation command of SDRAM 10. For example, a mode register set command is issued when signals CS#, RAS#, CAS# and WE# are low. When the mode register set command is issued, current data on the address terminals A0.about.A11 are transferred to and stored in the mode register 40 via address buffer 30. The mode register 40 is used to store access parameters, such as the burst length, the burst type and the CAS latency. A bank activation command must be issued before any read and write command. The bank activation command is triggered when signals CS# and RAS# are low, and signals CAS# and WE# are high. At this time, All (BS) is used to select the accessed memory bank and current data on A0.about.A10, referred as a column address, which is transmitted to selected bank-A row/column decoder 50 or bank-B row/column decoder 55. After the bank activation command, a read command or a write command can follow. The read command is set when CS# and CAS# are low, and RAS# and WE# are high. In addition, the write command is set when CS#, CAS# and WE# are low, and RAS# is high. Within a read or write command, a column address is input by A0.about.A10. The access memory location in bank-A memory 52 or bank-B memory 57 is determined by the row address provided by the bank activate command and the column address provided by the read or write command. This memory location is then accessible by means of data input/output DQ via input/output buffer 60.
When a new row access command or a new bank access command is issued, SDRAM requires a pre-charge operation to pre-charge bit-line pairs before sensing and amplifying data from the selected memory locations. Pre-charge is usually implemented by a dedicated circuit for each bank. Generally, SDRAMs support two pre-charge schemes, one is to issue an independent pre-charge command to the SDRAMs, and another is to issue a read or write command with pre-charge function. When an access command with pre-charge function is issued, the pre-charge operation will be automatically executed near the end of data bursting sequences. Traditional SDRAM must pre-charge the whole memory bank even though only one page is accessed. Cleanly, the pre-charge requirement may limit the issue of the next command and lower the operation speed. For example, when the write operation with auto-precharging function is executed, the bank undergoing auto-precharge can not be re-activated until a reference delay, called the data-in to active delay t.sub.DAL, is satisfied. The operation speed is inevitably affected by the undue delay.